Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■PCI (Peripheral Component Interface)
Target Models with PCI bus
Term PCI (Peripheral Component Interface)
o The PC-9800 series with PCI bus uses Intel's i82430LX (Mercury) chipset,
i82430NX (Neptune) chip, i????? (Orion) chipset, and VLSI Technologies' 82C594
(Wildcat) chipset as PCI chipsets.
The 82430 consists of two local bus accelerators 82433 (LBX) and a PCI,
memory, and cache controller 82434 (PCMC). The i82430LX is used with the 60MHz
Pentium processor, and the i82430NX is used with the 90MHz and 100MHz Pentium processors.
o The PC-9821Cf does not have a PCI bus, but uses the Mercury chipset as the
memory and cache controller.
o The configuration of the CPU, PCMC, LBX, PCI bus, etc. on a machine equipped
with a PCI bus is as shown in Figure 1.
Figure 1: Block diagram
--------------------------------------------------------------------
+-----------+
|CPU(Pentium|
|Processor) |
+-----+-----+
|
-----------+-----+--------------------+---------------Host CPU bus
| |
+---------+ +--+--+ +------+ +--+--+
|2nd cache+---+PCMC +---+Memory+---+ LBX |
+---------+ +--+--+ +------+ +--+--+
|*0 |
----------+------+------+-------------+-----+---------PCI bus
|*1 |*2 |*3
+----+----+ +------+-----+ +------+-----+
|PCI-C bus| |PCI-local | |PCI slot 0 | ･･･
|Bridge | |Bus bridge | +------------+
+----+----+ +------+-----+
| |
| ------+------+---------- ････ ------98 Graphics
| | Local Bus
| +--+--+
| |GVRAM|
| +-----+
|
---+------+-----+-------+-- ････ ---------+-----------C Bus
| | | |
+--+--+ +--+--+ +------+------+
|DMAC | | FDC | | C Bus Slot | ････
+-----+ +-----+ +-------------+
*0 PCMC is connected as device number 00000b
*1 PCI-C Bus Bridge is connected as device number 00001b
*1 PCI-Local Bus Bridge is connected as device number 00010b
*3 PCI slots #0-2 are connected as device numbers 01000-01010b
----------------------------------------------------------------------
o Mercury chipsets cannot use configuration mechanism #1, so they must use
configuration mechanism #2. Neptune chipsets can use either configuration mechanism.
o Configuration mechanism #1 specifies the PCI configuration address at I/O
0CF8h (DWORD) of the 82434NX (PCMC), and accesses the PCI configuration
register at I/O 0CFCh. (Figures 2 and 3)
o Configuration mechanism #2 accesses the PCI configuration registers mapped
to the CPU's I/O C000-CFFFh space. However, since only devices in the device
number range 00000-01111b are mapped, devices in the device number range
10000-11111b cannot be accessed. However, in a normal PCI bus, device numbers
start at 00000b, and it is rare for more than 16 PCI devices to exist on a
single PCI bus, so this restriction can be ignored in practice. (Figures 4 and 5)
Figure 2: Configuration mechanism #1 Type 0
---------------------------------------------------------------------
・Host-to-PCI Address Mapping for a Type0 Configuration Cycle
I/O 0CF8h(DWORD)
ConfigurationAddressRegister
31 24|23 16|15 11|108|7 2|10
1???????|00000000|XXXXX|YYY|ZZZZZZ|??
/ | | |
/ || | |
/ | | | |
/ | | | |
/ | | | |
/ | | | |
/ | | | |
/ | | | |
31 16|15 11|108|7 2|10
PCI address AAAAAAAAAAAAAAAA|BBBBB|CCC|DDDDDD|00
| | | ↓
| | | Configuration register number
| | |
| | |
| | ↓
| | Function number
| |
| ↓
| Reserved
↓
IDSEL# Select
Only the bits corresponding to the 4 bits of the device number
are set to 1, and the other 15 bits are set to 0
* This occurs when I/O 0CF8h bits 24 to 15h are 00000000b
---------------------------------------------------------------------
Figure 3: Configuration Mechanism #1 Type1
---------------------------------------------------------------------
・Host-to-PCI Address Mapping for a Type1 Configuration Cycle
I/O 0CF8h(DWORD)
ConfigurationAddressRegister
31 24|23 16|15 11|108|7 2|10
1???????|WWWWWWWW|XXXXX|YYY|ZZZZZZ|??
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
31 | 16|15 11|108|7 2|10
PCI Address 00000000|AAAAAAAA|BBBBB|CCC|DDDDDD|01
| | | ↓
| | | Configuration register number
| | |
| | |
| | ↓
| | Function number
| |
| ↓
| Device number
↓
Bus number
* Occurs when I/O 0CF8h bits 24 to 15h are not 00000000b
---------------------------------------------------------------------
Figure 4: Configuration mechanism #2 Type0
---------------------------------------------------------------------
・Host-to-PCI Address Mapping for a Type0 Configuration Cycle
15 12|11 8|7 2|
CPU I/O address (C000-CFFFh) 1100|XXXX|YYYYYY|
/ /| |
/ / | |
/ / | |
/ / | |
/ / | |
/ / | |
/ / | |
31 16|1511|108|7 2|10
PCI address AAAAAAAAAAAAAAAA|BBBB|CCC|DDDDDD|00
| | | ↓
| | | Configuration register number
| | | (Corresponds directly to CPU I/O address)
| | ↓
| | Function number
| | (I/O 0CF8h bit3〜1)
| ↓
| Reserved
↓
IDSEL# Select
Only the bits corresponding to the 4 bits from
bit 11 to 8 of the CPU I/O address will be 1,
and the other 15 bits will be 0
* This occurs when I/O 0CFAh (FORWARD REGISTER) is 00h
---------------------------------------------------------------------
Figure 5: Configuration mechanism #2 Type1
---------------------------------------------------------------------
・Host-to-PCI Address Mapping for a Type1 Configuration Cycle
15 12|11 8|7 2|
CPU I/O address (C000-CFFFh) 1100|XXXX|YYYYYY|
/ /| |
/ / | |
31 24|23 16| |1411|108|7 2|10
PCI address AAAAAAAA|BBBBBBBB|0|CCCC|DDD|EEEEEE|01
| | | | ↓
| | | | Configuration register Number
| | | | (Corresponds directly to CPU I/O address)
| | | ↓
| | | Function number
| | | (I/O 0CF8h bit3-1)
| | ↓
| | Agent number
| | (corresponding to CPU I/O address)
| ↓
| Bus number
| (I/O 0CFAh)
↓
Reserved
* Occurs when I/O 0CFAh (FORWARD REGISTER) is 01 to FFh
---------------------------------------------------------------------
o In the PC-9800 series using the 82430 chipset, the device numbers are set on the PCI bus as follows:
Table 1: IDSEL Decode Relationship
--------------+------------------+---------------+-------------
Device Number | Device | Vendor ID | Device ID
--------------+------------------+---------------+-------------
00000b | 82434(PCMC) | 8086h(Intel) | 04A3h(PCMC)
00001b | C Bus Bridge | 1033h(NEC) | 0001h
00010b | Local Bus Bridge | 1033h(NEC) | 0002h
01000b | PCI Slot #0 | |
01001b | PCI Slot #1 | |
01010b | PCI Slot #2 | | Xt only
--------------+------------------+---------------+-------------
o On the PC-9821Xa16, Xa13, Xa12, Xa10, Xa9, Xa7, and Xv13, device numbers are
set as follows on the PCI bus:
Table 2: IDSEL Decode Relationship
--------------+----------------------+----------------+-------------
Device Number | Device | Vendor ID | Device ID
--------------+----------------------+----------------+-------------
00000b | Wildcat | 1004h(VLSI) | 0007h(Wildcat)
00110b | C-bus Bridge | 1033h(NEC) | 0001h
00111b | 98 Graphics | 1033h(NEC) | 0009h
01000b | Internal Accelerator | 1023h(Trident) | 9660h(TGUI9680XGi)
01011b | PCI Slot #0 | |
01100b | PCI Slot #1 | |
--------------+----------------------+----------------+-------------
o On the PC-9821Xa7e, Xb10, V10, and V7/S, the device numbers are set as follows on the PCI bus:
Table 2: IDSEL Decode Relationship
--------------+-----------------------------+----------------+-------------
Device Number | Device | Vendor ID | Device ID
--------------+-----------------------------+----------------+-------------
00000b | PCMC | 1004h(VLSI) | 0007h(Wildcat)
00101b | Built-in Accelerator Bridge | 1033h(NEC) | 0016h
00110b | C Bus Bridge | 1033h(NEC) | 0001h
00111b | 98 Graphics | 1033h(NEC) | 0009h
01011b | PCI Slot #0 | |
--------------+-----------------------------+----------------+-------------
o In the PC-9821Xt16 and Xt13, the device numbers are set on the PCI bus as follows.
Table 2: IDSEL Decode Relationship
--------------+----------------------+----------------+-------------
Device Number | Device | Vendor ID | Device ID
--------------+----------------------+----------------+-------------
00000b | PCMC | 1004h(VLSI) | 0007h(Wildcat)
00110b | C-bus Bridge | 1033h(NEC) | 0001h
00111b | 98 Graphics | 1033h(NEC) | 0009h
01000b | SCSI Host Adapter | 9004h(Adaptec) | 7078h(AIC-7870)
01011b | PCI Slot #0 | |
01100b | PCI Slot #1 | |
01101b | Accelerator Slot | |
--------------+----------------------+----------------+-------------
o In the PC-9821Nx, the device numbers are set on the PCI bus as follows.
--------------+----------------------+----------------+-------------
Device number | Device | Vendor ID | Device ID
--------------+----------------------+----------------+-------------
00000b | Eagle | 1004h(VLIS) | Not investigated
00010b | 98 Graphics | 1033h(NEC) | Not investigated
00011b | Built-in accelerator | 1023h(Tridnet) | 9320h Cyber9320
00101b | C bus bridge | 1033h(NEC) | Not investigated
--------------+----------------------+----------------+-------------
o In the PC-9821Na9 and Na12, the device numbers are set on the PCI bus as follows.
--------------+-----------------+----------------+-------------
Device number | Device | Vendor ID | Device ID
--------------+-----------------+----------------+-------------
00000b | MobileTiton | 8086h(Intel) | 1235h
00010b | 98 Graphics | 1033h(NEC) | 0009h
00011b | Bus accelerator | 1023h(Tridnet) | 9320h Cyber9320
00101b | C-bus bridge | 1033h(NEC) | 0001h
--------------+-----------------+----------------+-------------
In the PC-9800 series, the interrupt signal pins INTA to INTD from the PCI
board are wired to different interrupt signal lines on the PCI bus depending
on the slot. This is to simplify interrupt routing on single function boards
that only use the INTA signal line. The correspondence for each slot is as follows.
Table 3: IDSEL decode relationship
----------------+-------+-------+-------+-------
Slot | INTA | INTB | INTC | INTD
----------------+-------+-------+-------+-------
Slot #0 | PIRQ0 | PIRQ1 | PIRQ2 | PIRQ3
Slot #1 | PIRQ1 | PIRQ2 | PIRQ3 | PIRQ0
Slot #2 | PIRQ2 | PIRQ3 | PIRQ0 | PIRQ1
----------------+-------+-------+-------+-------
Figure 6: Interrupt signal line connection (conceptual diagram)
----------------------------------------------------------------------
+-----------+
Interrupt←------| |-PIRQ0-----+-------+---------INTA-- +---------+
Controller←-----| Interrupt |-PIRQ1---+-|-------|-----+---INTB-- | PCI |
To controller←--| Router |-PIRQ2---|-|---+---|---+-|---INTC-- | Slot#0 |
←--| |-PIRQ3---|-|-+-|---|-+-|-|---INTD-- +---------+
←--| | | | | | | | | |
+-----------+ | | | | | | | +---INTA-- +---------+
| | | | | | +-----INTB-- | PCI |
| | | | | +-------INTC-- | Slot #1 |
| | | | +---------INTD-- +---------+
| | | |
| | | +-------------INTA-- +---------+
| | +---------------INTB-- | PCI |
| +-----------------INTC-- | Slot #2 |
+-------------------INTD-- +---------+
-----------------------------------------------------------------------
o In the PC-9800 series, the C-bus bridge device includes an interrupt router.
The PCI configuration register of the C-bus bridge device can be used to set
which interrupt input signal of the 8259 interrupt controller each of the
PIRQ0 to 3 signal lines is assigned to. This is usually set at startup by the
Plug and Play BIOS.
u The PC-9821Xt13 has three PCI bus slots, one of which is a slot dedicated to
the window accelerator board, and a card equivalent to the window accelerator
board X2 (PC-9821X-B03) is inserted into it. This slot does not have some of
the PCI bus signal lines, so cards that become PCI bus masters cannot be used.
Cards that do not become PCI bus masters can be used in the slot dedicated to
the window accelerator board.
o The PCI bus installed in the PC-9800 series is a standard in terms of
hardware, as defined by the standard. In other words, in terms of hardware, it
is possible to use PCI expansion boards made for IBM PC-AT compatible machines
with the PC-9800 series.
o PCI expansion boards for the PC-9800 series include the following:
-------------+----------------------------------------+-----------------+---------------
Model name | Product name | Vendor ID | Device ID
-------------+----------------------------------------+-----------------+---------------
PC-9821X-B01 | Full color window accelerator board X | 102Bh(Matrox) | 0518h(MGA-II)
PC-9821X-B02 | SCSI-2 interface board | 9004h(Adaptec) | 7178h (AIC-7870)
PC-9821X-B03 | Full color window accelerator board X2 | 102Bh(Matrox) | 0519h(Millennium)
SV-98/2-B03 | SCSI-2 interface board | 9004h(Adaptec) | 7178h(AIC-7870)
SV-98/2-B04 | SCSI-2 interface board | 1000h(NCR) | ????h(53C720)
SV-98/2-B05 | B4680 interface board EC | 1022h(AMD) | 2000h(AM79C970)
SV-98/2-B05L | B4680 interface board EC | 1022h(AMD) | 2000h(AM79C970)
SV-98/2-B06 | B4680 interface board ET | 1022h(AMD) | 2000h(AM79C970)
SV-98/2-B06L | B4680 interface board ET | 1022h(AMD) | 2000h(AM79C970)
-------------+----------------------------------------+-----------------+---------------
Related INT 1Ah - Function B1h
INT 1Fh - Function CCh
F8E8:0004h bit 5
I/O 0CF8h(BYTE)
Name CONFIGURATION SPACE ENABLE REGISTER(CSE)
Undocumented
Target Models with PCI bus
Function
[READ/WRITE]
bit 7-4: KEY
0000b = Normal Mode
0001-1111b = Configuration Mode
bit 3-1: FN
* Sets the value to be output to bits 10-8 of the PCI address.
bit 0: Reserved (must be 0)
Explanation o Controls whether to map the PCI configuration register on the
CPU's I/O C000-CFFFh address space. When KEY is other than 0000b, the PCI
configuration register is projected onto the I/O C000-CFFFh space.
o Valid only when configuration mechanism #2 is selected on the 82434NX.
Related I/O 0CFAh(BYTE)
I/O 0CFBh(BYTE) bit 7■[82434NX]
I/O 0CF9h(BYTE)
Name TURBO-RESET CONTROL REGISTER(TRC)
Undocumented
Target 82434LX/NX
Function
[READ/WRITE]
bit 7-4: Reserved
bit 3: CPU BIST Enable
1 = Enabled
0 = Disenabled
bit 2: Reset CPU
bit 1: System Hard Reset Enable
bit 0: Turbo/Deturbo Mode
1 = Deturbo
0 = Turbo
Explanation o Controls the 'TURBO mode' of IBM PC-AT compatible machines.
o Resets the CPU.
I/O 0CFAh(BYTE)
Name FORWARD REGISTER
Undocumented
Target PCI bus equipped models
Function
[READ/WRITE]
bit 7〜0: Forward Bus Number
00h = No Bus Forwarding
* Access to PCI Bus connected to PCMC
01h〜FFh = Bus Forwarding
* Bus[7:0] map to AD[23:16]
Explanation o Sets the mapping method for the PCI configuration register.
If 00h is specified, a Type 0 configuration cycle will be generated.
If any other value is specified, a Type 1 configuration cycle will be
generated, allowing access to devices on PCI buses other than bus number 00h.
o Only valid when configuration mechanism #2 is selected for the 82434NX.
Related I/O 0CF8h(BYTE)
I/O 0CFBh(BYTE) bit 7■[82434NX]
I/O 0CFBh(BYTE)
Name Configuration Mechanism Select
Undocumented
Target 82434NX
Function
[READ/WRITE]
bit 7: Configuration Mechanism #1 Enable
1 = Enable
0 = Disable
bit 6-0: Reserved(always 0000000b)
Explanation o Selects the configuration mechanism.
o To use configuration mechanism #1, bit 7 must be 1. When bit 7 is 0, I/O
0CF8h, 0CF9h, 0CFAh are compatible with 82434LX (Mercury chipset) and use
configuration mechanism #2 to access the PCI configuration register.
Related I/O 0CF8h(DWORD)
I/O 0CFCh
I/O 0CF8h (DWORD)
Name CONFIGURATION ADDRESS REGISTER
Undocumented
Target PCI bus equipped models (excluding PC-9821Xf)
Function
[READ/WRITE]
bit 31: Configuration Enable (CONE)
1 = Enable
0 = Disable
bit 15-24: Reserved (always 0000000b)
bit 23-16: BusNumber
bit 15-8: Device/Function Number
bit 7-0: ConfigurationRegisterOffset
Explanation o Specifies the PCI configuration register in configuration mechanism #1.
o To use configuration mechanism #1 that uses I/O 0CF8-0CFBh as the
configuration address register, bit 31 must be 1. When bit 31 is 0, I/O 0CF8h,
0CF9h, 0CFAh are compatible with 82434LX (Mercury chipset).
o Access to the configuration address register must be double word access from
I/O 0CF8h. Byte and word access to I/O 0CF8h, 0CF9h, 0CFAh, 0CFBh are treated
as normal I/O access.
Related I/O 0CFCh
I/O 0CFCh
Name CONFIGURATION DATA REGISTER
Undocumented
Target PCI bus equipped models (excluding PC-9821Xf)
Function
[READ/WRITE]
bit 31-0: Configuration Register Data
Explanation o Accesses the PCI configuration register specified by I/O 0CF8h in configuration mechanism #1.
o To use configuration mechanism #1, I/O 0CFCh bit 31 must be 1.
o While configuration mechanism #1 is specified, access to the configuration
data register can be either byte access, word access, or double word access.
Related I/O 0CF8h